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Project Development in XILINX ISE 10. 1

Chapter 4


A design engineer in digital industry uses hardware description language to keep rate with the output of the opponents. With VHSIC (HIGH Velocity Integrated Circuits) Hardware Explanation Terms (VHDL) we can easily illustrate and synthesize circuits of thousands of gates. In addition VHDL supplies the capabilities referred to as follows:

Power and versatility:

VHDL has powerful language constructs with which to write succinct code information of complicated control logic. It also has multiple degrees of design information for managing design implementation. It supports design libraries and creation of reusable components. It offers Design hierarchies to make modular designs. It really is one vocabulary fort design and simulation.

Device -Individual design:

VHDL permits to make a design without having to first choose a tool foe implementation. With one design description, we can target many device architectures. Without having to be acquainted with it, we can maximize our design for learning resource or performance. It enables multiple style of design explanation.


VHDL portability permits to simulate the same design description that people have synthesized. Simulating a big design information before synthesizing can save considerable time. As VHDL is a typical, design description can be taken from one simulator to another, one synthesis tool to some other; one system to another-means description can be used in multiple jobs.

Benchmarking functions:

Device-independent design and portability allows benchmarking a design using different device architectures and various synthesis tool. We can have a complete design description and synthesize it, create reasoning for it, evaluate the results and finally choose the device-a Organic Programmable Reasoning Device (CPLD) or a Field Programmable Gate Array (FPGA) that will fit our requirements.

ASIC Migration:

The efficiency that VHDL produces, allows our product to hit the market quickly if it's been synthesized over a CPLD or FPGA. When production value extends to appropriate levels, VHDL helps the development of Software Specific Integrated Circuit (ASIC). Sometimes, the exact code used with the Programmable Logic Device (PLD) can be used with the ASIC and because VHDL is a well-defined terms, we can be reassured that out ASIC merchant will deliver a device with expected features.


In the search of a typical design and documents for the High Speed Integrated Circuits (VHSIC) program, america Department of Security (DOD) in 1981sponsored a workshop on Hardware Description Languages (HDL) at Woods Hole, Massachusetts. In 1983, the DOD founded requirements for a standard VHSIC Hardware Explanation Language VHDL, its environment and its own software was awarded to IBM, Texas Devices and Intermetrics businesses.

VHDL 2. 0 premiered only following the project was begun. The vocabulary was significantly upgraded correcting the shortcoming of the sooner types; VHDL 6. 0 was released in 1984. VHDL 1078/1164 formally became the IEEE standard Hardware Description Vocabulary in 1987.

A VHDL design is defined as an 'entity declaration' and since an associated 'structures body'. The declaration specifies its program and can be used by architecture physiques of design entities at upper degrees of hierarchy. The structures body explains the operation of your design entity by specifying its interconnection with other design entities -'structural information, ' by its behavior -'behavioural information', or by an assortment of both. The VHDL vocabulary groupings, sub programs or design entities by use of deals.

For customizing general explanations of design entities, configurations are widely-used. VHDL also helps libraries possesses constructs for accessing deals, design entities or configurations from various libraries.

4. 2 Launch TO XILINX ISE 10. 1:

Create a New Project

Create a fresh ISE project which will aim for the FPGA device on the Spartan-3 Startup Package demo board.

To create a new project:

  1. Select File > New Task. . . The New Task Wizard appears.
  2. Type training in the Job Name field.
  3. Enter or search to a spot (directory path) for the new project. A tutorial subdirectory is established automatically.
  4. Verify that HDL is selected from the Top-Level Source Type list.
  5. Click Next to go to the device properties page.
  6. Fill in the properties in the table as shown below:
  • Product Category: All
  • Family: Spartan3
  • Device: XC3S200
  • Package: Feet256
  • Speed Level: -4
  • Top-Level Source Type: HDL
  • Synthesis Tool: XST (VHDL/Verilog)
  • Simulator: ISE Simulator (VHDL/Verilog)
  • Preferred Language: Verilog (or VHDL)
  • Verify that Enable Enhanced Design Overview is picked.

Leave the default ideals in the remaining fields.

When the table is complete, assembling your project properties can look like the following:



7. Click Next to proceed to the Create New Source window in the brand new Project Wizard. At

the end of another section, your brand-new task will be complete.

Create an HDL Source

In this section, you will generate the top-level HDL file for your design. Determine the terms that you wish to use for the tutorial. Then, continue either to the "Creating a

VHDL Source" section below, or skip to the "Building a Verilog Source" section.

Creating a VHDL Source

Create a VHDL source apply for the project as follows:

  1. Click the New Source button in the brand new Project Wizard.
  2. Select VHDL Module as the source type.
  3. Type in the record name counter.
  4. Verify that the Add to project checkbox is picked.
  5. Click Next.
  6. Declare the ports for the counter design by filling in the slot information as shown below:



7. Click Next, then Finish in the New Source Wizard - Summary dialog box to complete the new source file template.

8. Click Next, then Next, then Finish.

The source document formulated with the entity/structures pair displays in the Workspace, and the counter-top displays in the foundation tabs, as shown below:


Checking the Syntax of the New Counter Module

When the source data files are complete, check the syntax of the look to find mistakes and typos.

  1. Verify that Implementation is chosen from the drop-down list in the Resources window.
  2. Select the counter design source in the Options window to display the related techniques in the Functions window.
  3. Click the "+" next to the Synthesize-XST process to increase the process group.
  4. Double-click the Check Syntax process.

Note: You must correct any errors found in your source data. You can check for problems in the

Console tab of the Transcript windowpane. If you continue without valid syntax, you will not have the ability to simulate or synthesize your design.

5. Close the HDL document.

Design Simulation

Verifying Functionality using Behavioral Simulation

Create a test bench waveform formulated with type stimulus you may use to confirm the features of the counter component. The test bench waveform is a graphical view of an test bench.

Create the test bench waveform the following:

1. Select the counter HDL record in the Options window.

2. Create a fresh test bench source by selecting ProjectNew Source.

3. In the brand new Source Wizard, go for Test Bench Wave Form as the source type, and type

Counter_tbw in the File Name field.

4. Click Next.

5. The Associated Source webpage implies that you are associating the test bench waveform

with the source file counter-top. Click Next.

6. The Synopsis page demonstrates the foundation will be put into the task, and it displays

the source listing, type, and name. Click Finish.

7. You will need to create the clock regularity, set up time and productivity delay times in the Initialize.

Timing dialog package prior to the test bench waveform editing and enhancing window opens.

The requirements because of this design will be the following:

  1. The counter-top must operate appropriately with an insight clock regularity = 25 MHz.
  2. The DIRECTION type will be valid 10 ns prior to the rising advantage of CLOCK.
  3. The productivity (COUNT_OUT) must be valid 10 ns following the rising edge of CLOCK.

The design requirements correspond with the ideals below.

Fill in the domains in the Initialize Timing dialog container with the next information:

  1. Clock High Time: 20 ns.
  2. Clock Low Time: 20 ns.
  3. Input Setup Time: 10 ns.
  4. Output Valid Hold off: 10 ns.
  5. Offset: 0 ns.
  6. Global indication: GSR(FPGA).

Note: When GSR(FPGA) is empowered, 100 ns. is put into the Offset value automatically.


8. Click Finish to complete the timing initialization.

9. The blue shaded areas that precede the rising advantage of the CLOCK match the Input

Setup Time in the Initialize Timing dialog package. Toggle the Course port to determine the

input stimulus.


Note: For additional accurate alignment, you can use the Zoom In and Zoom Out toolbar control keys.

10. Save the waveform.

11. Within the Sources window, choose the Behavioral Simulation view to see that the test bench

waveform document is automatically put into assembling your project.



12. Close the test bench waveform.

Simulating Design Functionality

Verify that the counter design functions as you expect by performing tendencies simulation the following:

1. Verify that Behavioral Simulation and counter_tbw are decided on in the Options window.

2. Inside the Processes tab, click the "+" to increase the Xilinx ISE Simulator process and double-click the Simulate Behavioral Model process.

The ISE Simulator opens and runs the simulation to the finish of the test bench.

3. To see your simulation results, choose the Simulation tab and focus in on the transitions.



Note: You are able to dismiss any rows that start with TX.

4. Verify that the counter is counting along needlessly to say.

5. Close the simulation view. If you're prompted with the next message, "You might have an active simulation open. Are you sure you want to close it?" click Yes to continue.

You have finally completed simulation of your design using the ISE Simulator.

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